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? semiconductor ml9222 1/25 fedl9222-02 general description the ml9222 is a full cmos controller/driver for duplex or triplex vacuum fluorescent display tube. it conststs of 32-segment driver outputs and 3-grid pre-driver outputs, so that it can drive directly up to 96-segment vfd. ml9222 features a digital dimming function, a 8-ch adc, a 5 5 keyscan circuit and an encoder type switch interface. ml9222 provides an interface with a microcontroller only by four signal lines: data i/o, clock, cs and int. features ? supply voltage (v dd ) : 8 to 18.5v (built-in 5v regulator for logic) ? duplex/triplex selectable ? applicable vfd tube : 2 grids 32 anodes vfd tube : 3 grids 32 anodes vfd tube ? 32-segment driver outputs : i oh =C5ma at v oh =v dd C0.8v (seg1 to 22) i oh =C10ma at v oh =v dd C0.8v (seg23 to 32) ? 3-grid pre-driver outputs : i ol =10ma at v ol =2v ? built-in digital dimming circuit (10-bit resolution) ? built-in 8-ch a/d converter ? built-in 5 5 keyscan circuit ? 3 interface circuits for an encoder type rotary switch ? built-in oscillation circuit (external r and c) ? built-in power-on-reset circuit ? package: 80-pin plastic qfp (qfp80-p-1420-0.80-bk) product name: ML9222GA ? semiconductor ml9222 32-bit duplex/triplex vfd controller/driver with digital dimming, adc and keyscan fedl9222-02 this version: feb. 2000 previous version: nov. 1999
? semiconductor ml9222 2/25 fedl9222-02 block diagram timing generator dim out sync out1 sync out2 dup/ tri osc control out1-32 32bit shift register in1-10 dimming latch out1-10 10bit digital dimming por cs clock data i/o out1-3 3bit shift register por por por 4h out1-32 segment latch 3 in1-32 0h 3h por out1-32 segment latch 2 in1-32 0h 2h por out1-32 segment latch 1 in1-32 0h 1h por mode select in1-3 por 0h 7h 5v regulator & power on reset v cc (5v) l-gnd por out1-32 96 to 32 segment control in1-32 in1-32 in1-32 32 segment driver d-gnd v dd 3 grid pre driver grid2 grid3 grid1 seg32 seg1 vreg (5v) 5 5 key scan and encoder switch interface int 8ch, 8bit a/d converter osco ch1 ch8 col1 col5 row1 row5 a1 b1 5h 6h 7h a2 b2 a3 b3
? semiconductor ml9222 3/25 fedl9222-02 pin configuration (top view) vreg 41 ch1 42 ch2 43 ch3 44 ch4 45 ch5 46 ch6 47 ch7 48 ch8 49 seg1 50 seg2 51 seg3 52 seg4 53 seg5 54 seg6 55 seg7 56 seg8 57 seg9 58 seg10 59 seg11 60 seg12 61 seg13 62 seg14 63 v dd 64 dim out 40 sync out1 39 sync out2 38 nc 37 cs 36 clock 35 data i/o 34 l-gnd 33 nc 32 osc0 31 v cc 30 dup/ tri 29 nc 28 int 27 b1 26 a1 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 b2 a2 b3 a3 col5 col4 col3 col2 col1 row5 row4 row3 row2 row1 d-gnd grid3 grid2 grid1 seg32 seg31 seg30 seg29 seg28 v dd 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 seg15 seg16 seg17 nc seg18 seg19 seg20 nc seg21 seg22 seg23 seg24 nc seg25 seg26 seg27 nc: no connection 80-pin plastic qfp
? semiconductor ml9222 4/25 fedl9222-02 pin descriptions pin type description 1, 64 power supply pins. pin1 and pin64 should be connected externally. 10 33 50 to 63, 65 to 67, 69 to 71, 73, 74 o d-gnd is ground pin for the vfd driver circuit. l-gnd is ground pin for the logic circuit. pins 8 and 26 should be connected externally. segment (anode) signal output pins for a vfd tube. these pins can be directly connected to the vfd tube. external circuit is not required. i oh C5 ma 75, 76, 78 to 80, 2 to 6 o segment (anode) signal output pins for a vfd tube. these pins can be directly connected to the vfd tube. external circuit is not required. i oh C10 ma 7, 8, 9 o inverted grid signal output pins. for pre-driver, the external circuit is requiend. i ol 10 ma 36 i chip select input pin. data input/output operation is valid when this pin is set at a high level. 35 i serial clock input pin. data is input and/or output through the data i/o pin at the rising edge of the serial clock. 34 i/o serial data input/output pin. data is input to / comes out from the shift register at the rising edge of the serial clock. 29 i duplex/triplex operation select input pin. duplex (1/2 duty) operation is selected when this pin is set at a v cc level. triplex (1/3 duty) operation is selected when this pin is set at a gnd level. symbol v dd d-gnd l-gnd seg1 to 22 seg23 to 32 grid1 to 3 cs clock data i/o dup/ tri 30 o v cc 5v output pin for internal logic portion and external logic circuit. 41 o v reg reference voltage (5v) output pin for a/d converter. 27 o interrupt signal output to microcontroller. when any key of key matrix is pressed or released, key scanning is started. after the completion of the one cycle, this pin goes to high level and keeps the high level until keyscan stop mode is selected. int 21 to 26 i input pin for the encoder type rotary switch. each input has chattering absorption function of 620ns typical. a1 to a3 b1 to b3 42 to 49 i ch1 to 8 analog voltage input pin for the 8-bit a/d converter. 16 to 20 i return inputs from the key matrix. these pins are active low. when key matrix are in the inactive sate, these pins are at high level through the internal pull-up resistors. all the inputs do not have the cahttering absorption function for the keyscans. col1 to 5 11 to 15 o key switch scanning outputs. normally low level is output through these pin. when any switch of key matrix is depressed or released, key scanning is started and is continued until keyscan stop mode is selected. when keyscan stop mode is selected, all outputs of row1 to 5 go back to low level. row1 to 5
? semiconductor ml9222 5/25 fedl9222-02 pin type description 38, 39 o synchronous signal input. connect these pins to the sync in1 and sync in2 pins of a slave side. symbol sync out 1, 2 31 i/o rc oscillator connecting pins. connect a resistor (r2) between the v cc and osc0 pins, and a capacitor (c2) between the osc0 pin and the gnd, and a capacitor (c3) between the v cc and the gnd. c 3 is for v cc stabilization. osc0 v cc osc0 r 2 c 3 c 2 40 o dimming pulse output. connect this pin to the slave side dim in pin. dim out
? semiconductor ml9222 6/25 fedl9222-02 absolute maximum ratings recommended operating conditions parameter symbol v dd driver supply voltage v ih high level input voltage v il low level input voltage f c clock frequency t op operating temperature condition min. typ. max. unit 8.0 13.0 18.5 v all inputs except osc0 3.8 5.5 v all inputs except osc0 0.0 0.8 v 1.0 mhz C40 +85 c f osc oscillation frequency r 2 = 10k w 5%, c 2 = 27pf5% 2.6 3.3 4.0 mhz f fr frame frequency 1/3 duty 211 269 325 hz 1/2 duty 317 403 488 hz r 2 = 10k w 5% c 2 = 27pf5% parameter symbol condition rating unit v dd v supply voltage v in v input voltage p d ta = 85c mw power dissipation t stg c storage temperature i o1 seg1 to 22 ma i o2 seg23 to 32 ma output current i o3 grid1 to 3 ma i o4 dim out, sync out1, sync out2 ma C0.3 to +20 C0.3 to +6.0 764 C55 to +150 C10.0 to +2.0 C20.0 to +2.0 C7.0 to +20.0 C2.0 to +2.0
? semiconductor ml9222 7/25 fedl9222-02 electrical characteristics dc characteristics parameter symbol v ih high level input voltage v il low level input voltage i ih1 high level input current i il1 low level input current v oh1 v oh2 v oh3 high level output voltage condition min. max. unit 3.8 5.5 v 0.0 0.8 v v ih =3.8v C5.0 +5.0 m a v il =0.0v C5.0 +5.0 m a v dd C0.8 v dd v v dd C0.8 v dd v v dd C0.8 v dd v 4.0 5.5 v v dd =9.5v applied pin *1) *1) *2) *2) seg1 to 22 seg23 to 32 grid1 to 3 v oh4 *4) i oh1 =C5ma i oh2 =C10ma i oh3 =C5ma i oh4 =C200 m a v ol1 v ol2 v ol3 low level output voltage 2.0 v 2.0 v 2.0 v 0.8 v v dd =9.5v seg1 to 22 seg23 to 32 grid1 to 3 v ol4 *5) i ol1 =500 m a i ol2 =500 m a i ol3 =10ma i ol4 =300 m a 10ma i dd v dd supply current f osc =3.3mhz, no load (ta=C40 to +85c, v dd =8.0 to 18.5v) 4.5 5.5 v v l v cc supply voltage for logic c 3 =0.01 m f10%, i o =0 to C10ma 4.5 5.5 v output open i ih2 i il2 v ih =3.8v C100 C5.0 m a v il =0.0v C300 C70 m a *3) *3) *1) cs, clock, data i/o dup/ tri , a1 to a3, b1 to b3, col1 to 5 *2) cs, clock, data i/o dup/ tri , a1 to a3, b1 to b3 *3) col1 to 5 *4) data i/o, int, dim out, sync out1, sync out2 *5) data i/o, int, dim out, sync out1, sync out2, row1 to 5
? semiconductor ml9222 8/25 fedl9222-02 ac characteristics parameter symbol f c clock frequency t cw clock pulse width t ds data setup time t dh data hold time t csl cs off time t css t r t prz cs setup time (cs-clock) output slew rate time v dd rise time condition min. max. unit 1.0 mhz 400 ns 400 ns 400 ns r2=10k w 5%, c2=27pf5% 20 m s 400 ns t r =20% to 80% 4.0 m s t f =80% to 20% 4.0 m s mounted in a unit 100 m s c l =100pf t csh cs hold time (clock-cs) 400 ns t pof v dd off time mounted in a unit, v dd =0.0v 5.0 ms t pd data output delay time (clock-data i/o) 1.0 m s t f (ta=C40 to +85c, v dd =8.0 to 18.5v) t rsoff cs wait time 400 m s
? semiconductor ml9222 9/25 fedl9222-02 timing diagram data input timing C3.8v C0.8v C3.8v C0.8v C3.8v C0.8v cs clock data i/o (input) t ds t dh t css 1/f c t cw t cw t csh t csl valid valid valid valid reset timing t pof t prz v dd cs t rsoff C0.8v dd C0.0v C3.8v C0.0v C0.8v dd C0.2v dd seg1-32, grid1-3 t r t f data output timing C3.8v C0.8v C3.8v C0.8v C3.8v C0.8v cs clock data i/o (output) t pd t css t csh driver output timing
? semiconductor ml9222 10/25 fedl9222-02 a/d converter characteristics keyscan characteristics keyscan timing parameter a/d conversion accuracy condition typ. max. unit 1 lsb reference voltage (v reg ) 5.0 5.5 v output current C10 ma input voltage range v reg v conversion time/channel r2 = 10k w 5%, c2 = 27pf5% 310 min. 4.5 gnd 256 394 m s (ta = C40 to +85c, v dd = 8.0 to 18.0 v) parameter keyscan cycle time condition typ. max. unit r2 = 10k w 5%, c2 = 27pf5% 194 246 m s keyscan pulse width r2 = 10k w 5%, c2 = 27pf5% 39 min. 160 32 49 m s (ta = C40 to +85c, v dd = 8.0 to 18.0 v) row1 row5 row2 row3 row4 keyscan cycle time keyscan pulse width
? semiconductor ml9222 11/25 fedl9222-02 output timing (duplex operation) *1bit time=4/f osc (the dimming data is 1016/1024) grid1 v dd d-gnd grid2 v dd d-gnd grid3 seg1-32 v dd d-gnd dim out 5 v l-gnd sync out1 5 v l-gnd sync out2 5 v l-gnd v dd d-gnd 2048bit times (1 display cycle) 1016bit times 1016bit times 1016bit times 1019bit times 1019bit times 1019bit times 1019bit times 1019bit times 1019bit times 1029bit times 1019bit times 1019bit times 1019bit times 1029bit times 1029bit times 5bit times 5bit times 5bit times 3bit times 8bit times 8bit times 8bit times 5bit times 5bit times 5bit times 5bit times 5bit times 5bit times 5bit times 5bit times 5bit times output timing (triplex operation) *1bit time=4/f osc (the dimming data is 1016/1024) grid1 v dd d-gnd grid2 v dd d-gnd grid3 seg1-32 v dd d-gnd dim out 5 v l-gnd sync out1 5 v l-gnd sync out2 5 v l-gnd v dd d-gnd 3072bit times (1 display cycle) 1016bit times 1016bit times 1019bit times 1019bit times 1019bit times 1019bit times 1019bit times 1019bit times 1029bit times 1019bit times 1019bit times 1019bit times 1029bit times 5bit times 5bit times 5bit times 3bit times 8bit times 8bit times 5bit times 5bit times 5bit times 5bit times 5bit times 5bit times 5bit times 5bit times 5bit times 1019bit times 1016bit times 8bit times
? semiconductor ml9222 12/25 fedl9222-02 output timing (duplex operation) *1bit time=4/f osc (the dimming data is 64/1024) grid1 v dd d-gnd grid2 v dd d-gnd grid3 seg1-32 v dd d-gnd dim out 5 v l-gnd sync out1 5 v l-gnd sync out2 5 v l-gnd v dd d-gnd 2048bit times (1 display cycle) 64bit times 960bit times 960bit times 960bit times 64bit times 64bit times 957bit times 67bit times 957bit times 67bit times 957bit times 67bit times 3bit times 957bit times 67bit times 957bit times 67bit times 957bit times 67bit times 957bit times 1981bit times 1981bit times 957bit times 67bit times 957bit times 957bit times 67bit times 957bit times 1981bit times 957bit times 67bit times output timing (triplex operation) *1bit time=4/f osc (the dimming data is 64/1024) grid1 v dd d-gnd grid2 v dd d-gnd grid3 seg1-32 v dd d-gnd dim out 5 v l-gnd sync out1 5 v l-gnd sync out2 5 v l-gnd v dd d-gnd 3072bit times (1 display cycle) 64bit times 960bit times 960bit times 64bit times 957bit times 67bit times 957bit times 67bit times 957bit times 67bit times 3bit times 960bit times 64bit times 957bit times 67bit times 957bit times 67bit times 957bit times 67bit times 957bit times 1981bit times 957bit times 67bit times 67bit times 957bit times 957bit times 67bit times 957bit times 1981bit times 957bit times 67bit times
? semiconductor ml9222 13/25 fedl9222-02 functional description power-on reset when power is turned on, ml9222 is initialized by the internal power-on reset circuit. the status of the internal circuit after initialization is as follows: ? the contents of the shift registers and latches are set to "0". ? the digital dimming duty cycle is set to "0". ? all segment outputs are set to low level. ? all grid outputs are set to high level. ? all the row outputs are set to low level. ? int output is set to low level. data input and output data input and output through the data i/o pin is valid only when the cs pin is set at a high level. the input data to data i/o pin is shifted into the shift register at the rising edge of the serial clock. the data is automatically loaded to the latches when the cs pin is set at a low level. 10-bit dimming data (d1 to d10) and 32-bit segment data (s1 to s32) are used for inputting of dimming data and display data. to transfer these two data, the mode data (m0 to m2) must be sent after each of these data succeddingly. the output data from the data i/o pin is output from the shift register at the rising edge of the serial clock. ml9222 outputs 64-bit (8ch 8bits) a/d data (a11 to a88) and 37-bit key data (s11 to s55, r1, q11 to q13, r2, q21 to q23, r3 and q31 to q33). to receive these data, the mode data (m0 to m2) mast be sent first and then cs must be set once to low level and set again to high level. then inputting serial clocks, these data are output from the data i/o pin. when the cs pin is set at a low level, the data i/o pin returns to an input pin. to stop the keyscan, the only mode data (m0 to m2) must be sent. after the mode data transfer, the key scanning is stopped immediately. mode data ml9222 has the seven function modes. the function mode is selected by the mode data (m0 to m2). the relation between function mode and mode data (m0 to m2) is as follows: function mode operating mode function data m0 m1 m2 000 0 segment data for grid1-3 input 100 1 segment data for grid1 input 010 2 segment data for grid2 input 110 3 segment data for grid3 input 001 4 digital dimming data input 101 5 keyscan stop 011 6 switch data output 111 7 a/d data output
? semiconductor ml9222 14/25 fedl9222-02 segment data input [function mode: 0 to 3] ? ml9222 receives the segment data when function mode 0 to 3 are selected. ? the same segment data is transferred to the 3 segment data latch correspond to grid 1 to 3 at the same time when the function mode 0 is selected. ? the segment data is transferred to only one segment data latch that is selected by mode data, when the function mode is 1, 2 or 3 is selected. ? segment output (seg1 to 32) becomes high level when the segment data (s1 to 32) is high level. [data format] input data : 35 bits segment data : 32 bits mode data : 3 bits 1 s1 2 s2 3 s3 4 s4 29 s29 30 s30 31 s31 32 s32 33 m0 34 m1 35 m2 bit input data segment data (32bits) mode data (3bits) [bit correspondence between segment output and segment data] 1 s1 17 s17 2 s2 18 s18 3 s3 19 s19 4 s4 20 s20 5 s5 21 s21 6 s6 22 s22 7 s7 23 s23 8 s8 24 s24 9 s9 25 s25 10 s10 26 s26 11 s11 27 s27 12 s12 13 s13 14 s14 15 s15 16 s16 seg n segment data seg n segment data 28 s28 29 s29 30 s30 31 s31 32 s32
? semiconductor ml9222 15/25 fedl9222-02 digital dimming data input [function mode: 4] ? ml9222 receives the digital dimming data when function mode 4 is selected. ? the output duty changes in the range of 0/1024 (0%) to 1016/1024 (99.2%) for each grid. ? the 10-bit digital dimming data is input from lsb. [data format] input data : 13 bits digital dimming data: 10 bits mode data : 3 bits 1 d1 2 d2 3 d3 4 d4 7 d7 8 d8 9 d9 10 d10 11 m0 12 m1 13 m2 bit input data digital dimming data (10bits) mode data (3bits) 5 d5 6 d6 d10 0 0 1 1 1 1 d9 0 0 1 1 1 1 d8 0 0 1 1 1 1 d7 0 0 1 1 1 1 d6 0 0 1 1 1 1 d5 0 0 1 1 1 1 d4 0 0 0 1 1 1 d3 0 0 1 0 0 1 d2 0 0 1 0 0 1 d1 0 1 1 0 1 1 dimming data (msb) (lsb) duty cycle 0/1024 1/1024 1015/1024 1016/1024 1016/1024 1016/1024 lsb msb
? semiconductor ml9222 16/25 fedl9222-02 keyscan stop [function mode: 5] ? ml9222 stops a key scanning when function mode 5 are selected. ? to select this mode, the only mode data (m0 to m2) is needed. ? the actual time lag range between receipt of the keyscan stop command and the ceasing of scanning is 2.4 m s to 3.6 m s [input data format] input data : 3 bits mode data : 3 bits switch data output [function mode: 6] ? ml9222 output the switch data when function mode 6 is selected. ? to select this mode, the only mode data (m0 to m2) is needed. ? when ml9222 recieves this mode, the data i/o pin is changed to an output pin. ? 37-bit switch data come out from the data i/o pin synchronizing with the rise edge of the clock. ? when the cs pin is set at the low level, the data i/o pin returns to an input pin. ? r1, r2, r3=0, implies right rotation of the knob (clockwise) ? r1, r2, r3=1, implies left rotation of the knob (counter clockwise) ? contact count bits are q11 (lsb) to q13 (msb), q21 (lsb) to q23 (msb) and q31 (lsb) to q33 (msb) [input data format] input data : 3 bits mode data : 3 bits [output data format] output data : 37 bits 5 5 push swithc data : 25 bits encoder switch data : 12 bits 28 m0 29 m1 30 m2 bit input data mode data (3bits) 28 m0 29 m1 30 m2 bit input data mode data (3bits) 1 s11 26 r1 2 s12 27 q11 3 s13 28 q12 4 s14 29 q13 5 s15 30 r2 6 s21 31 q21 7 s22 32 q22 8 s23 33 q23 9 s24 34 r3 10 s25 35 q31 11 s31 36 q32 12 s32 37 q33 13 s33 14 s34 15 s35 16 s41 17 s42 18 s43 19 s44 20 s45 21 s51 22 s52 23 s53 24 s54 25 s55 bit output data bit output data sij:i=row1 to 5, j=col1 to 5 sij=1: switch on sij=0: switch off
? semiconductor ml9222 17/25 fedl9222-02 a/d data output [function mode: 7] ? ml9222 output the a/d data when function mode 7 is selected. ? to select this mode, the only mode data (m0 to m2) is needed. ? when ml9222 recieves this mode, the data i/o pin is changed to an output pin. ? 64-bit a/d data come out from the data i/o pin synchronizeing with the rise edge of the clock. ? when the cs pin is set at the low level, the data i/o pin returns to an input pin. [input data format] input data : 3 bits mode data : 3 bits [output data format] output data : 64 bits a/d data : 64 bits 28 m0 29 m1 30 m2 bit input data mode data (3bits) 1 a11 (lsb) 2 a12 3 a13 4 a14 ch1 5 a15 6 a16 7 a17 8 a18 (msb) 9 a21 (lsb) 10 a22 11 a23 12 a24 ch2 13 a25 14 a26 15 a27 16 a28 (msb) a31 (lsb) a38 (msb) a41 (lsb) a48 (msb) a51 (lsb) a58 (msb) a61 (lsb) a68 (msb) bit output data a/d 17 18 a32 19 a33 20 a34 ch3 21 a35 22 a36 23 a37 24 25 26 a42 27 a43 28 a44 ch4 29 a45 30 a46 31 a47 32 bit output data a/d 33 34 a52 35 a53 36 a54 ch5 37 a55 38 a56 39 a57 40 41 42 a62 43 a63 44 a64 ch6 45 a65 46 a66 47 a67 48 bit output data a/d a71 (lsb) a78 (msb) a81 (lsb) a88 (msb) 49 50 a72 51 a73 52 a74 ch7 53 a75 54 a76 55 a77 56 57 58 a82 59 a83 60 a84 ch8 61 a85 62 a86 63 a87 64 bit output data a/d
? semiconductor ml9222 18/25 fedl9222-02 the rotary encoder switch function. as figure 1 shows, the rotary encoder switch circuit is consisted of phase detection, interrupt generation, up/down counter, direction latch and parallel-in serial-out shift register. fig.1 the rotary encoder switch circuit 1) phase detection 1-1) clockwise the input a and b have a chattering absorption circuit of 620ns (typ.). when signal a and b input as fig. 2, the phase detection circuit outputs up signal after the chattering absorption period. at this time, the output int also goes to high level, so this signal can be used as an interrupt. the int stays high level until the switch data-output mode is selected. fig.2 the input and output timing in case of clockwise. phase detection up down b q3 q2 q1 a up/down counter p-in/s-out shift registor r1 direction latch interrupt generation for int output data up (internal) b a int chattering absorption time
? semiconductor ml9222 19/25 fedl9222-02 2) up/down counter when the up/down counter is input up, it counts up and when it is input down, it counts down. but if overcounte of "111" occurs the up/down counter stays "111". fig.4 3) direction latch when the direction latch is input down the output r goes "1". but if the up pulse is input and the counts value change to plus value, the output r goes to "0". fig.5 fig.3 the input and output timing in case of counter clockwise. down (internal) b a int chattering absorption time b q3, q2, q1 a 001 010 011 100 101 110 111 111 b q1, q2, q3 a 010 100 100 100 000 010 r1 1-2) counter clockwise when signal a and b input as fig. 3, the phase detection circuit outputs down signal after the chattering absorption period. at this time, the output int also goes to high level. the int stays high level until the switch data-output mode is selected.
? semiconductor ml9222 20/25 fedl9222-02 4) p-in/s-out shift resistor when the switch data output mode is selected and sc goes l, all the key data send to the shift resistor, and the up/down counter is reset and the int signal goes "l". fig.6 cs data i/o clock when cs goes l, the up/downn counter is reset and the int goes "l". int c2 c1 c4 c3 c1 c5 c3 c2 c5 c4 row1 row2 c2 c1 c4 c3 r1 c5 q11 q12 q13 r2 q21 q22 q23 r3 q31 q32 q33 row5 rotary
? semiconductor ml9222 21/25 fedl9222-02 keyscan keyscanning is started only when depression or release of any key is detected in order to minimize noise caused by scanning signal. then, keyscanning is continued until the keyscan stop mode is sent from a microcomputer. the int pin goes to the high level at the completion of 1-cycle scanning after the keyscan start, so the (high level) signal sent from the int pin can be used as an interrupt signal. [keyscan timing] 1 cycle int row 5 row 4 row 3 row 2 row 1 depress/release keyscan stop mode is selected. note: keyscanning cannot be stopped by selecting the keyscan stop mode only once if: - keyscanning is started after depression or release of any key is detected, and then - a key is depressed or released again before the keyscan stop mode is selected. to stop keyscanning, it is required to select the keyscan stop mode once again. depress depress release keyscan keyscan int cs mode5 mode5 mode5 mode5 : keyscan stop
? semiconductor ml9222 22/25 fedl9222-02 application circuits 1. circuit for the duplex vfd tube with 128 segments (2 grid 64 anode) ml9222 v dd v cc l-gnd osc0 v cc clock data i/o cs vreg dup/ tri dim out sync out 1 sync out 2 grid2 grid1 grid3 seg1 seg32 msm9210 (slave) v disp v dd l-gnd osc 0 osc 1 clock data in cs dim in sync in 1 sync in 2 dim out sync out 1 sync out 2 grid2 grid1 grid3 seg1 seg32 duplex vfd tube s62 s63 s64 s1 s2 s3 g1 g2 microcontroller v disp m/ s gnd dup/ tri ef gnd gnd gnd gnd ch1 to 8 row1 to 5 col1 to 5 5 5 key matrix
? semiconductor ml9222 23/25 fedl9222-02 2. circuit for the triplex vfd tube with 192 segments (3 grid 64 anode) ml9222 v dd v cc l-gnd clock data i/o cs dim out sync out 1 sync out 2 grid2 grid1 grid3 seg1 seg32 msm9210 (slave) v disp v dd l-gnd osc 0 osc 1 clock data in cs dim in sync in 1 sync in 2 m/ s dup/ tri dim out sync out 1 sync out 2 grid2 grid1 grid3 seg1 seg32 triplex vfd tube s62 s63 s64 s1 s2 s3 g1 g2 microcontroller v disp gnd ef gnd gnd gnd osc0 v cc gnd ch1 to 8 row1 to 5 col1 to 5 5 5 key matrix vreg g3 dup/ tri
? semiconductor ml9222 24/25 fedl9222-02 (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). qfp80-p-1420-0.80-bk package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 1.27 typ. mirror finish
? semiconductor ml9222 25/25 fedl9222-02 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third partys industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third partys right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. 9. ms-dos is a registered trademark of microsoft corporation. copyright 2000 oki electric industry co., ltd. printed in japan

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